IBM Sub-1 Nanometer Chip Signals AI Compute Leap

IBM on June 25, 2026 unveiled the IBM sub-1 nanometer chip, a 0.7 nm (7-angstrom) technology built on a three-dimensional nanostack transistor architecture. The company described it as a path to angstrom-level scaling with the potential to reshape AI compute.

Nanostack Design and Prototype

IBM introduced nanostack as the industry’s first three-dimensional, nanosheet-based transistor architecture. Unlike traditional chips that rely on shrinking features across the wafer surface, nanostack vertically stacks and staggers transistors, adding a third dimension to scaling. The design can pack nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm chip introduced in 2021.

The company demonstrated prototype devices on a wafer and presented technical details at the VLSI 2026 conference. Secondary technical reports describe the implementation as sequentially stacked complementary metal-oxide-semiconductor (CMOS) transistors with flexible placement of top and bottom nanosheet channels, ultra-thin dielectric bonding, and a thermally stable bottom transistor gate stack. IBM’s research showed functional nanosheet-on-nanosheet CMOS transistors and working CMOS inverters with electrical characteristics comparable to or better than non-stacked baselines.

IBM emphasized that transistor “nodes” are generational labels rather than exact physical dimensions but used the 0.7 nm designation to signal the extension of logic technology below 1 nm into angstrom-level scaling, where dimensions approach the size of individual atoms.

Performance and Commercial Outlook

IBM’s published technical results project the nanostack design to deliver up to 50% more performance or 70% greater energy efficiency compared with its 2 nm node chips. The company also highlighted about a 40% improvement in static random-access memory (SRAM) scaling, which it said is significant for high-bandwidth, memory-intensive AI systems.

IBM framed the technology as targeted at generative AI workloads, cloud infrastructure, and next-generation electronic devices. It described nanostack as a research-stage technology on a research-to-manufacturing path being developed at its semiconductor research facility in Albany, New York. The company said it sees a path to production in as early as five years and projects at least a decade of further scaling.

IBM has not disclosed specific manufacturing or commercialization partners for nanostack but continues to work with outside partners on its current nanosheet manufacturing efforts, including Rapidus. Jay Gambetta, head of IBM Research, predicted that chips built on nanostacking approaches could become prevalent in data centers within about ten years.

"IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms," the company said.